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<dc:title xml:lang="fr">Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques</dc:title>
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<dc:subject xml:lang="fr">3D-IC</dc:subject>
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<dc:subject xml:lang="fr">IPVD</dc:subject>
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<dc:subject xml:lang="fr">Barrière</dc:subject>
<dc:subject xml:lang="fr">Couche d’accroche</dc:subject>
<dc:subject xml:lang="fr">Caractérisation</dc:subject>
<dc:subject xml:lang="en">3D-IC</dc:subject>
<dc:subject xml:lang="en">TSV</dc:subject>
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<dc:subject xml:lang="en">Barrier layer</dc:subject>
<dc:subject xml:lang="en">Seed layer</dc:subject>
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<tef:elementdEntree autoriteExterne="031513824" autoriteSource="Sudoc">Dépôt en phase vapeur</tef:elementdEntree>
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<tef:elementdEntree autoriteExterne="027337510" autoriteSource="Sudoc">Microélectronique</tef:elementdEntree>
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<dcterms:abstract xml:lang="fr">Ces dernières années, l’évolution de la taille des circuits intégrés a été dirigée par la loi de Moore conduisant à des noeuds technologiques de 22 nm et en-deçà. Cependant, les problématiques de performances, de taille et de coût des composants rendent cette conjecture difficile à suivre. La tendance de diversification appelée « More than Moore » consiste à intégrer des fonctions analogiques avec des technologies CMOS dans le but d’optimiser les coûts.L'une de ses technologies clés est le TSV, qui maintient le contact entre deux niveaux de composants. Leurs facteurs de forme devenant de plus en plus élevés, les techniques de dépôts standards par iPVD sont proches de leurs limites. De plus, les méthodes de caractérisation usuelles ne sont pas adaptées à ces structures.La première partie de cette thèse sera dédiée au développement des procédés de dépôt de la barrière de diffusion du cuivre par MOCVD à basse température pour s’adapter aux divers schémas d'intégration de type via middle et via last. La deuxième partie sera consacrée à l’élaboration des protocoles avancés de caractérisation des films dans ces structures afin d’étudier leurs comportements en intégration.</dcterms:abstract>
<dcterms:abstract xml:lang="en">For the past years, Moore’s law has pointed mainstream microelectronics, driving integrated circuits down to 22 nm and below. Yet, performance, dimension and cost issues make it difficult to follow the trend. Integrating analog functions into CMOS-based technologies enables cost-optimized systems solutions. These diversified tendencies are known as “More than Moore”. One of the key technologies of this trend is the TSV, which maintains the contact between two components.The increasing aspect ratio of via made it critical to obtain a continuous, conformal coverage of the copper diffusion barrier layer using iPVD.In the first part of this thesis, a promising deposition technique by MOCVD has been developed at low temperature to fulfill various integration schemes including via last and via middle processes.Characterizations of the behavior of these materials in the TSV then became a great challenge in order to handle the integration protocol. Working at theses scales makes standard methods limited to evaluate the intrinsic properties inside the TSV. In the second part, the implementations of advanced characterization into these structures were carried out.</dcterms:abstract>
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